Electrostatic discharge is a 4 Billion (USD) a year problem for the Semiconductor Industry. This problem is likely to grow in the future as smaller devices are susceptible to damage at lower static voltages and latchup under more subtle conditions. Today, circuit designers and process integration engineers require a fundamental knowledge of device physics and electrothermal behavior of I/O structures in order to develop a process that is robust and can withstand the challenges of today’s varied environments in which ICs are fielded. Layout, ESD pulse behavior, semiconductor physics, and device modeling are all required to produce a successful product. Your industry needs competent engineers and scientists to help achieve these goals. ESD Design and Technology is a course that offers detailed instruction on a variety of subjects pertaining to ESD design and technology. This course is designed for every manager, engineer, and technician concerned with ESD at the I/O design level, the chip level, or supplying ESD tools and simulators to the industry.

Electrostatic Discharge (ESD) is a challenging issue with today's integrated circuit designs.  Scaling and new technology features make meeting ESD requirements a difficult proposition.  Furthermore, the variety of ESD standards can make meeting the requirements a confusing proposition.  Fundamentally, ICs need to be robust against damage.  In this course, we will cover the physics and models, how semiconductor processes affect ESD, the impact of advanced and future technologies on meeting ESD requirements, basic ESD circuits and how to design them, how to design input/output (I/O) networks to be robust to ESD, some case studies, and common ESD design tools.  By taking this course, technology and design engineers will gain insight into ESD and how to design technologies and circuits to be robust to ESD.